Dynamic Power Analysis
The power integrity based on a dynamic power analysis becomes the key sign-off factor for SoC yield enhancement. Multi-million gate design complexities, shrinking operating voltages and accelerating frequencies are the yield harassing factors in SoC design.

The more and more designs are facing the design failures which are explainable not in ordinary statistical analysis
but in dynamic analysis.

Proposed Power Analysis Tool`s overview
We propose new power analysis integrity method such as below picture. It is faster than traditional Dynamic Simulation
and Accuracy is better than Static Analysis method. We distribute clock events & Non clock events for speed up.
Using the varied clock scheduling methods, improves overall speed.