Current on-chip interconnect solution facing their limits
Shared bus is facing the performance and scalability limit
- connecting more components to the shared wire worsens the operating clock frequency
- increased load demands higher driving capacity of bus driver, which is not always possible or too costly

Single bus matrix solution also has its limitation on the applicable system size
- as the connectivity becomes complex, enlarged control logics push back the operating clock frequency
- due to enlarged control logic and increased load, required energy for unit data transfer increases

Distributed bus matrix solution and the topology synthesis for specific applications